Telecommunications network includes a variety of traffic control mechanisms. Policing mechanisms are those which monitor traffic streams and/or substreams to see if they conform to set parameters and/or to take any necessary actions in case of non conformance. Their action may involve, dropping or discarding packets which are out-of-profile (non-conforming), and marking or tagging packets in priority or colours.
A known policing mechanism employs a scheduling algorithm known as virtual scheduling algorithm (VSA for short). The VSA can be thought of as being split up into two parts, a conformance check part indicating whether or not a packet in a stream is to be discarded according to a VSA instance and an update part in which a basic parameter used by the VSA, e.g., the predicted arrival time, is updated as a function of the arrival time of a non-discarded packet.
A traffic stream in the telecommunications network is made up of series of packets (or cells in some instances) which may be of fixed or variable lengths. There are many traffic streams flowing in the network and two or more traffic streams may be arranged in a hierarchical structure. A packet, therefore, may belong to one or more traffic streams. Each traffic stream, in turn, may comprise either one or two substreams (e.g., high priority packet substream and aggregate substream containing both high and low priority packets). Therefore, in this example, a high priority packet also belongs to both substreams. Each substream has a single rate control and contains rate parameters (e.g., rate and burst tolerance), and policing state (e.g., predicted arrival time). One policing engine is required for each substream to which a packet belongs.
For example, an ATM cell stream contains high and low priority cells, indicated by the CLP bit. For such an ATM cell stream, the ITU-TS recommendation I.371 prescribes that the substream of high priority first cells is to be policed separately, whereas the aggregate ATM stream (or “aggregate substream” to be consistent in the usage of the term) of both first and second cells is also to be policed as a whole. One way to achieve this is to use a processing means in which two series connected processors each apply a specific police algorithm instance to a specific substream. The first processor thus operates according to an instance of a VSA on one substream that consists of the high priority first cells, whereas the second processor operates according to a similar VSA instance on the other substream which includes both unpoliced low priority second cells and policed high priority first cells.
U.S. Pat. No. 5,541,913 Jul. 30, 1996 Witters et al describes a policing device of the above known type but with a more generic architecture easily adaptable to a wide variety of distinct policing methods. The architecture therefore arranges multiple instantiations of police engines in parallel and is described to be easily adaptable to not only a large number of distinct policing methods for the ATM stream but also to those that may be realized as the result of subsequent changes to the ITU recommendation.
FIG. 1 illustrates schematically the policing device of the above patent.
Though described as applicable to arbitrary algorithms, the policing device includes a plurality of parallel police processors 10, 12, each of which implements a Modified Virtual Scheduling Algorithm (MVSA for short), which can in general be separated into two stages of processing: update and conformance. The update stage maintains the algorithm state (e.g., a cell's predicted arrival time). The conformance stage calculates whether the cell under evaluation is conformant to the algorithm. In other words, the cell's actual arrival time is later than the predicted arrival time, or stated differently the cell did not arrive earlier than the predicted arrival time. The policing device also has an enabling circuit 14 which activates one or both of the processors for each received cell of an ATM input stream and the processors then generate conformance signals. From the conformance signals, an arbitration module 16 generates a discard signal 18 and feedback signals 20, 22, the discard signal indicating whether or not such a cell may be inserted into an ATM output stream by a discard circuit and the feedback signals indicating to a corresponding processor whether or not to carry out an already prepared update of a predicted arrival time used in the above mentioned algorithm. By employing the arbitration module and the enabling circuit, the architecture allows implementation of many policing methods.
The above patent describes the MVSA as comprising the following code:
IF (PAT<TIME)THENTEMP_PAT:=TIME+NIATCS:=1ELSEIF (PAT>TIME+γ)THENTEMP_PAT:=PAT+NIATCS:=0ELSETEMP_PAT:=PAT+NIATCS:=1Wherein,
PAT is a predicted arrival time;
TIME is an arrival time of the handled cell;
TEMP_PAT is a prepared updated value of PAT;
γ is a so-called Cell Delay Variation tolerance;
NIAT is a negotiated cell inter-arrival time;
CS is a conformance value indicating whether or not the handled cell is conforming according to the applied instance of the MVSA. CS=1 is conformant and CS=0 is non-conformant.
The above MVSA is similar to the virtual scheduling algorithm mentioned earlier, except for some modifications. One of the modifications is that the predicted arrival time is not updated directly but that only an update is prepared for it in an intermediate variable TEMP_PAT. Whether or not this update is effectively applied then depends upon a feedback value, FS, in the following way:
IF (FS=1) THENPAT:=TEMP_PAT    ELSE   PAT:=PAT
Another modification consists in the introduction of a new line allowing for the preparation of an update value even when an instance of the MVSA finds the handled cell to be unsatisfactory. This modification is only needed in applying specific policing methods but is introduced in all cases in order to keep the policing device PD generic, i.e. to allow each and any policing method to be applied by it. It is also implemented by each of the police processors in order to be able to use identical police processors in the policing device.
The above MVSA is split up in a conformance check part, deriving the conformance signal and an update part, preparing an updated value TEMP_PAT and performing the update when instructed by feedback signals. Therefore, in carrying out an instance of the MVSA, the processors prepare the updated value TEMP_PAT and generate the resulting conformance values as the conformance signals. The arbitration module, on the other hand, generates feedback values which the processors use as feedback signals in carrying out the above instance of MVSA.
By defining the operation of the enabling circuit EC and the arbitration module AM, a number of distinct policing methods can be realized. For example, by designing the enabling circuit EC to activate both processors PP1 and PP2 for the high priority first cells and the second processor PP2 only for low priority second cells, the policing method satisfying the ITU-TS recommendation I.371 can be realized. As mentioned earlier, the recommendation states that the ATM stream (aggregate substream) including both high and low priority cells should be policed as a whole while the substream formed by the high priority cells should also be policed separately.
The patent describes a several other policing methods that can be realized by the architecture described therein. Instead of using the cell's arrival time, the described policing method can use a leaky bucket and its fill state to calculate if the packet is conformant. Although described as generic in the patent, the architecture cannot be configured to realize algorithms in which the update algorithm of one processor is a function of the update algorithm of the second processor. In the cases described in the above patent, PP1 and PP2 update independently of one another. The patent also describes the architecture in connection with ATM cell stream only. One of such algorithms which cannot be realized is described immediately below. As will be described in detail, that algorithm uses two leaky buckets and their updates are dependent on one another.
IETF RFC2697 describes a single rate, three colour dual leaky-bucket policing algorithm, called a single rate three colour marker. This policing algorithm is intended to condition variable length packet stream such as IP traffic, including MPLS, Frame Relay, voice/video over Internet etc. This algorithm requires two leaky buckets and the credit update algorithms of the two leaky buckets are codependent. RFC2697 states that this marker can be used as component in a differentiated services traffic conditioner. The algorithm meters a traffic stream (e.g., IP packet stream) and marks its packets either green, yellow, or red. Marking is based on three traffic parameters, Committed Information Rate (CIR), and two associated burst sizes, a Committed Burst Size (CBS) and Excess Burst Size (EBS). The CIR is measured in bytes of IP packets per second and includes the IP header, but not link specific headers. The CBS and EBS are measured in bytes. A packet is marked green if it does not exceed the CBS, yellow if it does exceed the CBS, but not the EBS, and red otherwise. This algorithm is useful, for example, for ingress policing of a service, where only the length, not the peak rate, of the burst determines service eligibility. There are two modes of operation, colour-blind and colour-aware modes.
FIG. 2 is a schematic block diagram of the algorithm for the colour blind mode of operation in which all the packets are treated as coloured green. As seen in FIG. 2, selection circuit 40 passes size, flow, time and colour (in colour aware mode) of a received packet to meter 42 which meters each packet and passes metering result to transmitting circuit 44, which performs action of pass (accept)/mark (Green, Yellow, Red)/drop as indicated by the metering result. The meter consists of two leaky buckets C and E, designated 46 and 48 respectively. Both buckets share the CIR. Conformance (metering) results 50 from the leaky buckets determine the colour of the packet. The conformance results and the fill states of the buckets are processed in a determination block 52 to determine which update function 54 or 56 is to be performed.
The algorithm operates as follows:
The maximum size of bucket C is CBS and that of bucket E is EBS. Tc and Te are bucket fill states of buckets C and E. At time 0, the two buckets are full, i.e., Tc(0)=CBS and Te(0)=EBS. After time 0, the fills of the two buckets, Tc and Te, are updated CIR times per second as follows:                if Tc is less than CBS, Tc is incremented by one, else;        if Te is less than EBS, Te is incremented by one, else;        neither Tc nor Te is incremented.        
When a packet of size B bytes arrives at time t, the following happens in the color-blind mode operation:                if Tc(t)−B>=0, the packet is green and Tc is decremented by B down to the minimum value of 0, else;        if Te(t)−B>=0, the packets is yellow and Te is decremented by B down to the minimum value of 0, else;        the packet is red and neither Tc nor Te is decremented.        
When a packet of size B bytes arrives at time t, the following happens in the color-aware mode operation:                if the packet has been precoloured as green and Tc(t)−B>=0, the packet is green and Tc is decremented by B down to the minimum value of 0, else;        if the packet has been precoloured as green or yellow and if Te(t)−B>=0, the packets is yellow and Te is decremented by B down to the minimum value of 0, else;        the packet is red and neither Tc nor Te is decremented.        
As seen above, in this example, each packet stream is controlled by two leaky buckets and their updating (incrementing or decrementing) depends on the state of the two leaky buckets. In particular, whether or not to update bucket E depends on both the states of bucket C and bucket E itself. The generic architecture described in the above mentioned patent cannot be configured to realize this type of algorithms that require multiple policing engines for each packet stream in which the update algorithm of one police engine is a function of the update algorithm of the next police engine and so on.